In the field of electronics, various electronic design automation (EDA) tools are useful in automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, application specific integrated circuits (e.g., ASICs), and in the design of an integrated circuit that may be programmable.
Verilog and VHDL (VHSIC Hardware Description Language) are conventional hardware description languages and are widely used to describe an integrated circuit design. VHDL, for example, is a hardware description language (HDL) used to design integrated circuits at the component, board, and system levels. VHDL allows models to be developed at a high level of abstraction. Similarly, Verilog is a hardware description language (HDL) used to design electronic systems at the component, board and system levels.
In designing an integrated circuit, an integrated circuit designer typically creates a netlist description of an integrated circuit. The netlist may be in the form of a hardware description language, such as Verilog, VHDL, or other suitable hardware description language.
A netlist generally describes the integrated circuit design and is typically stored in computer readable media and processed using well-known techniques. The netlist may include a list of logic gates and their interconnections, which make up the integrated circuit. One use of the netlist is the creation of a physical device layout in mask form, which can be used to directly implement structures in silicon to realize the physical integrated circuit.
During conventional development of an integrated circuit, however, there are many instances in which significant manual editing of the hardware description language netlist is necessary. These manual edits are typically cumbersome and may be error-prone and time-consuming.
For example, during development of an integrated circuit, it is common to make changes to a netlist in order to add test circuits for testing the associated integrated circuit described by the netlist. Later in the development process, it may be desirable to apply the same changes to a revised netlist, which may be an altered, or updated, version of the netlist. According to conventional approaches, in this situation, the revised netlist is manually edited to include the same changes originally made to the netlist. This manual editing of the revised netlist may be cumbersome, error-prone, and time-consuming.
Manual editing a netlist to include the same changes made to another netlist is, therefore, undesirable in that it may consume valuable development resources.